Menu

Open FPGA Remote Lab

 

Overview

The open FPGA remote lab developed is intended to perform distance VHDL programming practices with visualization through a WebCam. The main contribution of the lab is that it allows both local and remote compilation modes. Local compilation is available for those users that uses the Xilinx ISE Web Pack software installed in their computers. In this mode, users generate the binary file locally through the Xilinx environment and upload it to the remote lab. This mode offers more possibilities than the remote compilation mode, e.g., simulation tools and graphical interface. On the other side, the remote compilation is more educational. The student gets educational feedback of each FPGA compilation stage. The user only needs to write VHDL code in a regular text editor and upload it to the remote lab.

Regarding the access services, it provides authentication and scheduling services. The number of simultaneous users allowed to work concurrently in the lab is limited to ten. If this number is reached then another ten users can stay waiting for work in the waiting queue. Although ten students can work simultaneously in the lab, only one can execute files in the device at a time and get access to the video streaming from the cam. The rest of the users can work on the completion of the different stages involved in the .bit generation process, i.e., XST, nags-build, map, parse, trace, bit-generation.

The lab saves the student activity in logs (learning analytics) so that teachers can review and analyse their performance.

Finally, the system is open source, so that anyone can download the code and connect it to a Xilinx 3AN Spartan FPGA to have their own open FPGA remote lab.

 

Audience:

This remote lab may be of interest to any researcher interested on VHDL programming, FPGA, or reconfigurable devices and its educational applications, both for educational institutions and corporate training. This remote is interesting to those researchers that want to implement a FPGA remote lab but do not want to start from scratch, as this lab is open source.

 

Goals:

– Performing remote practices of VHDL programming with real instrumentation

– Understanding the foundations of FPGA programming

– Understanding the foundations of FPGA architecture

– Understanding the foundations of FPGA compilation process

 

Access:

The lab may be used in both english and Spanish.

Watch our demo video to understand how our FPGA Remote Lab works:

 

Open source:

Download the source code from our site in Sourceforge and participate in our open community to improve the lab.